Integrated circuit and semiconductor memory devices store information in arrays of cells arranged in addressable rows and columns. During fabrication of these devices, one or more defects may occur and hinder the proper performance of the memory circuit. Some types of defects may be analyzed and corrected on the device. Other types of defects may not be corrected and are the cause of failed devices. Distribution of defects in any memory device may be random. The yield of good devices per wafer can be improved over time by eliminating the causes of such defects.
As generations of new memory devices are designed and built, integrated circuit memories have increasing bit densities, smaller storage cell sizes, and more input/output (I/O) pins. As a result, devices are more susceptible to defects caused by processing variations and reduced tolerances. Testing has to be done to detect and correct the defects so that sufficiently high device yields are achieved for profitable production.
Additionally, it is desirable for semiconductor memories to have faster data I/O. One method of facilitating high speed data I/O within a semiconductor is to provide a subarray. The subarray is advantageous to use because data can be read from it at a faster speed than data from the main memory in the semiconductor memory.
One type of subarray is a serial access memory (SAM), which is used in video random access memory (VRAM) devices. The main memory and the SAM operate asynchronously. The main array and the SAM each have its own set of I/O pins. The main array and the SAM are functionally connected just during the transfer of data from the main array to the SAM or vice versa.
As with other integrated circuit memory devices, there exists the probability that a defect might occur during the manufacturing of the SAM. A defect can cause erroneous data to either be read or written from the SAM. Redundant cells exist in the SAM to replace defective addresses, similar to what is done in the main array. The problem, however, is being able to efficiently and quickly test for defects in the SAM.
Tests exist to test main memory devices. During testing to determine if there are any bit failures in the main memory, a limited number of I/O pins are connected to a device tester. Connecting fewer I/O pins to the device tester allows more devices to be tested in parallel. The standard approach has been to just connect I/O pins of the main memory to the device tester and test the main memory using on-chip comparison logic. However, there is a problem in using the I/O pins of the main memory and the on-chip comparison logic to test the SAM.